As silicon capabilities continue to increase, the ability to efficiently design and manufacture chips becomes increasingly critical to their deployment. The times required to build chips have begun to exceed the required time to market. The increasingly complex efforts relating to physical design of the chips have accorded a great sense of urgency on addressing “second order” effects to meet time-related goals. For instance, the resolution of minimum device features comparable to (or smaller than) the wavelength of the exposing light has made the lithography for mask making increasingly complex and expensive. All of these second order effects increase the cost of designing a chip to the point where only high volume chips are economically viable.
The industry has responded to this situation by initiating the development of System-On-a-Chip (SoC) methodologies. This approach integrates pre-designed or pre-verified components, called intellectual property (IP) components or cores, into single chip designs. For instance, an SoC may include IP components such as a central processing unit (CPU), a universal asynchronous receiver/transmitter (UART), an enhanced multiply/accumulate unit (EMAC), etc. Typically, an SoC design specification is hierarchical and the hierarchy clearly separates the IP components used in the SoC. However, many designs are processed by the design tools as a flat netlist, ignoring the SoC hierarchy. The design hierarchy is definitely flattened at the manufacturing phase. Accordingly, the reusability of an EP block is ignored during the manufacturing phase. Thus, even though the SoC approach partially addresses the design cost and complexity by means of re-use at the resistor-transistor logic (RTL) level, it fails to address the dramatically increasing costs related to mask data preparation and mask building.
U.S. Pat. No. 6,383,847 B1, entitled “Partitioned Mask Layout,” issued on May 7, 2002, to Ditlow et al., which is hereby incorporated by reference, teaches a mask reuse methodology (MRM) that utilizes reusable partitioned masks that provide “hard” logic to reduce the cost of making a mask set for an SoC device. In particular, the '847 patent teaches the idea of having a reusable mask set for a library of different EP components. Thus, when a chip requires one or more of these components, existing masks that correspond to the required components are used to create the component(s). Each component on the chip is thus fabricated as a partition in a separate fabrication step.
However, the '847 patent does not describe how to create a mask set for the soft logic for the chip. Soft logic refers to any logic that is not provided by a reusable mask set, including, e.g., glue logic that connects IP blocks, custom logic required for a customer's particular application, etc.
Accordingly, a need exists for an efficient process for creating a mask for the soft logic, and for utilizing the mask set of the IP blocks and the mask set for the soft logic to build a complete chip.